(1) Field of the Invention
The present invention relates to a method used to fabricate a storage node structure, for a DRAM capacitor structure, and more specifically to a method of optimizing a hemispherical grain silicon layer, prior to formation of an overlying capacitor dielectric layer.
(2) Description of the Prior Art
The major objectives of the semiconductor industry are to continually improve the performance of semiconductor devices, while still maintaining, or decreasing the cost of fabricating these same semiconductor devices. These objectives have been successfully addressed by the ability of the semiconductor industry to produce semiconductor chips with sub-micron features, or micro-miniaturization. Smaller features allow a reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source, of a source/drain region, of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of a billion cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
One method that has been used to increase STC capacitance, while still decreasing the lateral dimension of the capacitor, has been the use of rough, or hemispherical grain (HSG), silicon layers. The HSG silicon layer is comprised of convex and concave features, and when used as the top layer of the storage node structure, results in a greater degree of surface area then counterparts fabricated with smooth silicon layers. However the space between the convex and concave features, of the HSG silicon layer, can present difficulties when attempting to form a capacitor dielectric layer, uniformly on the underlying HSG silicon layer. If the spaces between HSG silicon features is to small to accept the desired thickness of the capacitor dielectric layer, a thinner than desired capacitor dielectric layer will formed, which can present yield and reliability concerns, in terms of dielectric leakage, or breakdown, during normal DRAM operating conditions.
This invention will describe a novel process preparing an HSG silicon layer, for formation of an overlying, capacitor dielectric layer. Prior to the formation of the capacitor dielectric layer, the HSG silicon layer is subjected to an isotropic etch, increasing the space between the HSG silicon layer, concave and convex features, thus allowing the formation of a uniform, in thickness, capacitor dielectric layer, to be realized.
Prior art such as Thakur et al, in U.S. Pat. No. 5,656,531, or Zahurak et al, in U.S. Pat. No. 5,639,685, describe processes for fabricating HSG silicon layers, however these prior art do not describe the isotropic etch procedure, applied to the HSG silicon layer, prior to the formation of the capacitor dielectric layer, allowing the formation of a uniform capacitor dielectric layer.